There is a constant demand to reduce the clock cycle time of a microprocessor in order to process more instructions per second. Attempts to meet the demand have included reduction in circuit element geometries and process-related improvements. Another way to meet the demand has been the use of dynamic logic, particularly in critical timing paths. However, even dynamically evaluated data signals must eventually be latched. The delay associated with a static latch may be a relatively large proportion of the clock cycle time (or half clock cycle time), which takes away from the remaining portion of the clock cycle time that may be used by dynamic logic to evaluate the data. Therefore, what is needed is a way to reduce the delay associated with latching dynamically evaluated data.